1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More specifically, the present invention relates to method and apparatus for improving uniformity of wafers during plasma processing in a semiconductor plasma processing system.
2. Description of the Related Art
Semiconductor processing systems are used to process semiconductor wafers for fabrication of integrated circuits. In particular, plasma-enhanced semiconductor processes are commonly used in etching, oxidation, chemical vapor deposition (CVD), etc. The plasma-enhanced semiconductor processes are typically carried out by means of plasma processing systems and generally include a plasma processing chamber to provide a controlled setting.
Conventional plasma processing chambers often include electrostatic chucks to hold a wafer (e.g., silicon wafer or substrate) in place for processing. Electrostatic chucks utilize electrostatic force to clamp the wafer to the chuck and are generally classified into monopolar and bipolar electrostatic chucks. Monopolar electrostatic chucks have a single pole whereas the bipolar electrostatic chucks have two poles. Electostatic chucks are well known in the art and are amply described, for example, in commonly owned U.S. Pat. No. 5,789,904 by Francois Guyot and entitled "High Power Electrostatic Chuck Contact," U.S. patent application Ser. No. 08/624,988 by Jones et al. and entitled "Dynamic Feedback Electrostatic Wafer Chuck," U.S. patent application Ser. No. 08/550,510 by Castro et al., and U.S. Pat. No. 5,793,192 by Kubly et al. and entitled "Methods and Apparatus for Clamping and Declamping a Semiconductor Wafer in a Wafer Processing System." The disclosures of these references are incorporated herein by reference.
FIG. 1 illustrates a cross-sectional view of an exemplary electrostatic chuck (ESC) 100 for clamping a wafer 102. The electrostatic chuck 100 includes dielectric layers 106 and 110, and a layer of electrode 108. The electrode 108 is disposed between the dielectric layers 106 and 108 and is configured as a pair of poles 108A and 108B in a bipolar ESC arrangement with an insulator provided therebetween.
The poles 108A and 108B are coupled to a positive and negative terminals of a power supply 112. Hence, the pole 108A is biased positively while the pole 108B is biased negatively. The bias potential of the poles 108A and 108B induces charges in the adjoining surface regions of the dielectric layers 106 and 110. For example, negative charges are induced on the bottom surface region 116 of the dielectric layer 106 that lies over the pole 108A. On the other hand, positive charges are induced at the upper surface region 118 of the dielectric layer 106 opposite of the bottom surface region 116. Similarly, positive charges are induced on the bottom surface region 120 of the dielectric layer 106 disposed over the pole 108B and negative charges build up on the opposite top surface region 122 of the dielectric layer 106.
The positive and negative charges on the top surface regions 118 and 122 of the dielectric layer 106, in turn, induce charges to be built up along the bottom surface regions 124 and 126 of the wafer 102. The induced potential between the dielectric layer 106 and the wafer 102 produces an electrostatic force that allows the wafer 102 to be clamped to the electrostatic chuck 100. With the wafer 102 clamped, plasma source gases are released into a plasma region 128 over the wafer for plasma processing such as etching, vapor deposition, sputtering, or the like until a desired degree of etching or deposition has been achieved.
Unfortunately, such plasma processes typically do not yield a uniform result due to non-uniform distribution of plasma over the wafer 102. For example, FIG. 2A shows an exemplary graph 200 depicting sputtering rate over a wafer. A curve 202 plots a sputtering rate of plasma over the radial distance from the center 204 of the wafer 102. As shown in the graph 200, the sputtering rate increases as the radial position nears the center 204 of the wafer. Conversely, the sputtering rate decreases as the radial distance of the wafer 102 increases from the center 204 and then increases sharply near the edge of the wafer.
The non-uniform distribution of plasma over the wafer typically produces a process result that is non-uniform across the entire surface of the wafer. FIG. 2B illustrates an etched surface 210 of a wafer after etching it in a conventional plasma processing chamber. Before the etching process, the surface of the wafer is assumed to be a uniform surface 212 for illustration purposes. After the etching process, the surface 210 of the wafer forms an upward incline from the center 214 of the wafer in either direction. In particular, the etched surface 210 shows that the center 214 of the wafer is etched more than neighboring regions due to greater concentration of plasma in the center region.
FIG. 2C shows deposition uniformity of a wafer surface over the radial distance after performing plasma deposition in a conventional plasma processing chamber. The dotted line 220 corresponds to the surface of the wafer before the plasma deposition. After the plasma deposition process, the resulting surface 222 of the wafer slopes downward from a peak at the center 224 of the wafer. The resulting surface 222 of the wafer generally reflects the plasma distribution or sputtering rate illustrated above in FIG. 2A. The non-uniform surface characteristics of wafers resulting from such plasma etching and deposition processes are undesirable because they reduce yield per wafer and throughput.
A traditional method has improved plasma uniformity by using a shower head with additional apertures or holes disposed over the sides of a wafer. These additional apertures or holes are designed to allow the shower head to release more plasma source gases. Hence, more plasma is produced in the regions located away from the center of the wafer, thereby compensating for lower plasma distribution in these regions. This approach, while improving process uniformity to a degree, is highly sensitive to the distance between the shower head and the wafer. For example, if the shower head is too far from the wafer, plasma source gases released from the shower head may not be uniformly distributed, thereby leading to non-uniform distribution of plasma. On the other hand, if the wafer is too close to the shower head, the plasma source gases may not have sufficient time to distribute uniformly.
Another solution has implemented a magnetic confinement ring around a shower head or an electrostatic chuck to confine the plasma within the area defined by the ring. By thus confining the plasma, the ring is designed to increase plasma concentration over the outer radial regions of the wafer. Unfortunately, however, the magnetic confinement ring often produces well-known cusp effect on the peripheral surface of the wafer due to the magnetic field of the confinement ring.
Furthermore, producing uniformly distributed plasma over a wafer may have the undesirable effect of reducing plasma density. This is because a wafer exposed to the reduced plasma density generally takes more time to produce a desired etch or deposition result than a wafer subject to a higher plasma density. Hence, the etch or deposition process may take longer to complete in a uniformly distributed plasma environment.
In view of the foregoing, what is needed is a method and apparatus for improving wafer processing uniformity during plasma processing without substantially increasing the processing time and without substantial sensitivity to the wafer distance from the source of plasma source gases